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FEATURES Isolation Test Voltage: To 3.5 kV rms Five Isolated Logic Lines: Available in Six I/O Configurations Logic Signal Bandwidth: 20 MHz (min) CMV Transient Immunity: 10 kV/ s min Waveform Edge Transmission Symmetry: 1 ns Field and System Output Enable/Three-State Functions Performance Rated Over -25 C to +85 C UL1950, IEC950, EN60950 Certification (VDE, CE, Pending) APPLICATIONS PLC/DCS Analog Input and Output Cards Communications Bus Isolation General Data Acquisition Applications IGBT Motor Drive Controls High Speed Digital I/O Ports
F0
High Speed, Logic Isolator AD261
FUNCTIONAL BLOCK DIAGRAM
THR STA EETE
LINE 0
LATCH D E LATCH D E LATCH D E
S0
F1
THR STA EETE
LINE 1
2 S1
F2
THR STA EETE
LINE 2
3 S2
F3
LATCH D E LATCH D E
LINE 3
EETHRATE ST
4
S3
F4
LINE 4
EETHRATE ST
5
S4
ENABLEFLD 17
6
ENABLESYS
GENERAL DESCRIPTION
+5V dcFLD 16 5V RTNFLD 15
+5V dc 5Vdc RTN
+5V dc
7
+5V dcSYS 5V RTNSYS
The AD261 is designed to isolate five digital control signals to/from a microcontroller and its related field I/O components. Six models allow all I/O combinations from five input lines to five output lines, including combinations in between. Every AD261 effectively replaces up to five opto-isolators. Each line of the AD261 has a bandwidth of 20 MHz (min) with a propagation delay of only 14 ns, which allows for extremely fast data transmission. Output waveform symmetry is maintained to within 1 ns of the input so the AD261 can be used to accurately isolate time-based PWM signals. All field or system output pins of the AD261 can be set to a high resistance three-state level by use of the two enable pins. A field output three-stated offers a convenient method of presetting logic levels at power-up by use of pull-up/down resistors. System side outputs being three-stated allows for easy multiplexing of multiple AD261s. The isolation barrier of the AD261 B Grade is 100% tested as high as 3.5 kV rms (system to field). The barrier design also provides excellent common-mode transient immunity from 10 kV/s common-mode voltage excursions of field side terminals relative to the system side, with no false output triggering on either side. Each output is updated within nanoseconds by input logic transitions, the AD261 also has a continuous output update feature that automatically updates each output based on the dc level of the input. This guarantees the output is always valid 10 s after a fault condition or after the power-up reset interval.
5Vdc RTN
8
FIELD TYPICAL MODEL
SYSTEM
(AD261-2)
PRODUCT HIGHLIGHTS
Six Isolated Logic Line I/O Configurations Available: The AD261 is available in six pin-compatible versions of I/O configurations to meet a wide variety of requirements. Wide Bandwidth with Minimal Edge Error: The AD261 affords extremely fast isolation of logic signals due to its 20 MHz bandwidth and 14 ns propagation delay. It maintains a waveform input-to-output edge transition error of typically less than 1 ns (total) for positive vs. negative transition. 3.5 kV rms Test Voltage Isolation Rating: The AD261 B Grade is rated to operate at 1.25 kV rms and is 100% production tested at 3.5 kV rms, using a standard ADI test method. High Transient Immunity: The AD261 rejects commonmode transients slewing at up to 10 kV/s without false triggering or damage to the device.
(Continued on page 5)
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997
AD261-SPECIFICATIONS (Typical at T = +25 C, +5 V dc
A
SYS,
+5 V dcFLD, tRR = 50 ns max unless otherwise noted)
Min Typ Max Units
Parameter INPUT CHARACTERISTICS Threshold Voltage Positive Transition (VT+) Negative Transition (VT-) Hysteresis Voltage (VH) Input Capacitance (CIN) Input Bias Current (IIN) OUTPUT CHARACTERISTICS Output Voltage1 High Level (VOH) Low Level (VOL) Output Three-State Leakage Current DYNAMIC RESPONSE (Refer to Figure 2) Max Logic Signal Frequency (fMIN) Waveform Edge Symmetry Error (tERROR) Logic Edge Propagation Delay (tPHL, tPLH) Minimum Pulsewidth (tPWMIN) Max Output Update Delay on Fault or After Power-Up Reset Interval ( 30 s)2 ISOLATION BARRIER RATING3 Operating Isolation Voltage (VCMV) Isolation Rating Test Voltage (VCMV TEST)4 Transient Immunity (VTRANSIENT) Isolation Mode Capacitance (CISO) Capacitive Leakage Current (ILEAD) POWER SUPPLY Supply Voltage (+5 V dcSYS and +5 V dcFLD) Power Dissipation Capacitance Quiescent Supply Current Supply Current TEMPERATURE RANGE Rated Performance (TA)5 Storage (TSTG)
1
Conditions
+5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V +5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V +5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V Per Input
2.0 3.0 0.9 1.2 0.4 0.5
2.7 3.2 1.8 2.2 0.9 1.0 5 0.5
3.15 4.2 2.2 3.0 1.4 1.5
V V V V V V pF A
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA +5 V dcSYS = 4.5 V, |IO| = 4 mA +5 V dcSYS = 4.5 V, |IO| = 0.02 mA +5 V dcSYS = 4.5 V, |IO| = 4 mA ENABLESYS/FLD @ Logic Low/High Level Respectively 50% Duty Cycle, +5 V dcSYS = 5 V tPHL vs. tPLH
4.4 3.7 0.1 0.4 0.5 20
V V V V A MHz ns ns ns s
1 14
25
25 12 AD261A AD261B AD261A AD261B Total Capacitance, All Lines 240 V rms @ 60 Hz Rated Performance Operating Effective, per Input, Either Side Effective per Output, Either Side--No Load Each, +5 V dcSYS & FLD All Lines @ 10 MHz (Sum of +5 V dcSYS & FLD) 4.5 4.0 8 28 4 18 -25 -40 +85 +85 375 1250 1750 3500 10,000 9 15 2 5.5 5.75
V rms V rms V rms V rms V/s pF A rms V dc V dc pF pF mA mA C C
NOTES 1 For best performance, bypass +5 V dc supplies to com., at or near the device (0.01 F). +5 V dc supplies are also internally bypassed with 0.05 F. 2 As the supply voltage is applied to either side of the AD261, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 s after the point where +5 V dc SYS & FLD passes above 3.3 V. 3 "Operating" isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be "hi-pot" tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but nondestructive). 4 Partial Discharge at 80 pC THLD. 5 Supply Current will increase slightly, but otherwise the unit will function within specification to -40C. Specifications are subject to change without notice.
-2-
REV. 0
AD261
ABSOLUTE MAXIMUM RATINGS*
Parameter Supply Voltage (+5 V dcSYS & FLD) DC Input Voltage (VIN MAX) DC Output Voltage (VOUT MAX) Clamp Diode Input Current (IIK) Clamp Diode Output Current (IOK) Output DC Current, per Pin (IOUT) DC Current, VCC or GND (ICC or IGND) Storage Temperature (TSTG) Lead Temperature (Soldering, 10 sec) Electrostatic Protection (VESD)
Conditions Referred to +5 V dcSYS & FLD and 5 V RTNSYS & FLD Respectively Referred to +5 V RTNSYS & FLD and 5 V dcSYS & FLD Respectively For VI < -0.5 V or VI > 5 V RTNSYS & FLD +0.5 V For VO < -0.5 V or VO > 5 V RTNSYS & FLD +0.5 V
Min Typ -0.5 -0.5 -0.5 -25 -25 -25 -50 -40 4.5 5
Max +6.0 +0.5 +0.5 +25 +25 +25 +50 +85 +300
Units V V V mA mA mA mA C C kV
Per MIL-STD-883, Method 3015
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
I/O CONFIGURATIONS AVAILABLE
PIN CONFIGURATION
1 2 3 4 5 SYSTEM 6 7 8 S0 S1 S2 S3 S4 ENABLESYS +5V dcSYS 5V RTNSYS
The AD261 is available in several configurations. The choice of model is determined by the desired number of input vs. output lines. All models have identical footprints with the power and enable pins always being in the same locations.
PIN FUNCTION DESCRIPTIONS Pin 1-5* 6 7 8 9-14 15 16 17 18-22* Mnemonic S0 Through S4 ENABLESYS +5 V dcSYS 5 V RTNSYS Function
Digital Xmt or Rcv from F0 Through F4 System Output Enable/Three-State System Power Supply (+5 V dc Input) System Power Supply Common Not Present On Unit 5 V RTNFLD Field Power Supply Common Field Power Supply (+5 V Input) +5 V dcFLD Field Output Enable/Three-State ENABLEFLD F0 Through F4 Digital Xmt or Rcv from S0 Through S4
BOTTOM VIEW
*Function of pin determined by model. Refer to Table I.
5V RTNFLD +5V dcFLD ENABLEFLD F0 F1 F2 F3 F4
15 16 17 FIELD 18 19 20 21 22
ORDERING GUIDE Model Number AD261AND-0 AD261AND-1 AD261AND-2 AD261AND-3 AD261AND-4 AD261AND-5 AD261BND-0 AD261BND-1 AD261BND-2 AD261BND-3 AD261BND-4 AD261BND-5 Description 0 Inputs, 5 Outputs 1 Input, 4 Outputs 2 Inputs, 3 Outputs 3 Inputs, 2 Outputs 4 Inputs, 1 Output 5 Inputs, 0 Outputs 0 Inputs, 5 Outputs 1 Input, 4 Outputs 2 Inputs, 3 Outputs 3 Inputs, 2 Outputs 4 Inputs, 1 Output 5 Inputs, 0 Outputs Isolation Ratings 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms Package Description Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Package Option ND-22A ND-22A ND-22A ND-22A ND-22A ND-22A ND-22A ND-22A ND-22A ND-22A ND-22A ND-22A
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD261 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-3-
AD261
AD261 CONFIGURATIONS
AD261-0
F0
THR STA EETE
LATCH
AD261-2
S0
F0
THR STA EETE
LINE 0
D E LATCH
LINE 0
LATCH D E LATCH D E LATCH D E
S0
F1
THR STA EETE
LINE 1
D E LATCH
2 S1
F1
THR STA EETE
LINE 1
2
S1
F2
THR STA EETE
LINE 2
D E LATCH
3 S2
F2
THR STA EETE
LINE 2
3
S2
F3
THR STA EETE
LINE 3
D E LATCH D E
4 S3
F3
LATCH D E LATCH D E
LINE 3
EETHRATE ST
4
S3
F4
THR STA EETE
LINE 4
5 S4
F4
LINE 4
EETHRATE ST
5
S4
ENABLEFLD 17 +5V dc 5V dc RTN +5V dc
6
ENABLESYS
ENABLEFLD 17 +5V dcFLD 16 5V RTNFLD 15 +5V dc 5V dc RTN +5V dc
6
ENABLESYS
+5V dcFLD 16 5V RTNFLD 15
7
+5V dcSYS 5V RTNSYS
7
+5V dcSYS 5V RTNSYS
5V dc RTN
8
5V dc RTN
8
FIELD
SYSTEM
FIELD
SYSTEM
AD261-1
LATCH
AD261-3
S0
F0
THR STA EETE
F0
THR STA EETE
LINE 0
D E LATCH
LINE 0
LATCH D E LATCH D E
S0
F1
THR STA EETE
LINE 1
D E LATCH
2
S1
F1
THR STA EETE
LINE 1
2
S1
F2
THR STA EETE
LINE 2
D E LATCH
3
S2
F2
LATCH D E LATCH D E LATCH D E
LINE 2
EETHRATE ST
3
S2
F3
THR STA EETE
LINE 3
D E
4 S3
F3
LINE 3
EETHRATE ST
4
S3
F4
LATCH D E
LINE 4
EETHRATE ST
5
S4
F4
LINE 4
EETHRATE ST
5
S4
ENABLEFLD 17 +5V dcFLD 16 5V RTNFLD 15 +5V dc 5V dc RTN +5V dc
6
ENABLESYS
ENABLEFLD 17 +5V dcFLD 16 5V RTNFLD 15 +5V dc 5V dc RTN +5V dc
6
ENABLESYS
7
+5V dcSYS 5V RTNSYS
7
+5V dcSYS 5V RTNSYS
5V dc RTN
5V dc RTN
8
8
FIELD
SYSTEM
FIELD
SYSTEM
-4-
REV. 0
AD261
AD261 CONFIGURATIONS
AD261-4
F0
THR STA EETE
AD261-5
S0 F0
LATCH D E LATCH D E LATCH D E LATCH D E LATCH D E
LINE 0
LATCH D E
LINE 0
EETHRATE ST
S0
LATCH
F1
D E LATCH
LINE 1
EETHRATE ST
2
S1
F1
LINE 1
EETHRATE ST
2
S1
F2
D E LATCH
LINE 2
EETHRATE ST
3
S2
F2
LINE 2
EETHRATE ST
3
S2
F3
D E LATCH
LINE 3
EETHRATE ST
4
S3
F3
LINE 3
EETHRATE ST
4
S3
F4
D E
LINE 4
EETHRATE ST
5
S4
F4
LINE 4
EETHRATE ST
5
S4
ENABLEFLD 17 +5V dcFLD 16 5V RTNFLD 15 +5V dc 5V dc RTN +5V dc
6
ENABLESYS
ENABLEFLD 17 +5V dcFLD 16 5V RTNFLD 15 +5V dc 5V dc RTN +5V dc
6
ENABLESYS
7
+5V dcSYS 5V RTNSYS
7
+5V dcSYS 5V RTNSYS
5V dc RTN
8
5V dc RTN
8
FIELD
SYSTEM
FIELD
SYSTEM
(Continued from page 1)
GENERAL ATTRIBUTES
Field and System Enable Functions: Both the isolated and nonisolated sides of the AD261 have ENABLE pins that threestate all outputs. Upon reenabling these pins, all outputs are updated to reflect the current input logic level. CE Certifiable: Simply by adding the external bypass capacitors at the supply pins, the AD261 can attain CE certification in most applications (to the EMC directive) and conformance to the low voltage (safety) directive is assured by the EN60950 certification.
Table I. Model Number and Pinout Function
Pin 1 2 3 4 5 6 7 8 9-14 15 16 17 18 19 20 21 22 AD261-0 S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Xmt) S4 (Xmt) ENABLESYS +5 V dcSYS 5 V RTNSYS 5 V RTNFLD +5 V dcFLD ENABLEFLD F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Rcv) F4 (Rcv) AD261-1 AD261-2 AD261-3 AD261-4 AD261-5 S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Xmt) S4 (Rcv) * * * * * * F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Rcv) F4 (Xmt) S0 (Xmt) S0 (Xmt) S1 (Xmt) S1 (Xmt) S2 (Xmt) S2 (Rcv) S3 (Rcv) S3 (Rcv) S4 (Rcv) S4 (Rcv) * * * * * * Not Present * * * * * * F0 (Rcv) F0 (Rcv) F1 (Rcv) F1 (Rcv) F2 (Rcv) F2 (Xmt) F3 (Xmt) F3 (Xmt) F4 (Xmt) F4 (Xmt) S0 (Xmt) S1 (Rcv) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * S0 (Rcv) S1 (Rcv) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * * * * F0 (Xmt) F1 (Xmt) F2 (Xmt) F3 (Xmt) F4 (Xmt)
The AD261 provides five HCMOS compatible isolated logic lines with 10 kV/s common-mode transient immunity. The case design and pin arrangement provides greater than 18 mm spacing between field and system side conductors, providing CSA/IS and IEC creepage spacing consistent with 750 V mains isolation. The five unidirectional logic lines have six possible combinations of "ins" and "outs," or transmitter/receiver pairs; hence there are six AD261 part configurations (see Table I). Each 20 MHz logic line has a Schmidt trigger input and a threestate output (on the other side of the isolation barrier) and 14 ns of propagation delay. A single enable pin on either side of the barrier causes all outputs on that side to go three-state and all inputs (driven pins) to ignore their inputs and retain their last known state. Note: All unused logic inputs (1-5) should be tied either high or low, but not left floating. Edge "fidelity," or the difference in propagation time for rising and falling edges, is typically less than 1 ns. Power consumption, unlike opto-isolators, is a function of operating frequency. Each logic line barrier driver requires about 160 A per MHz and each receiver 40 A per MHz plus, of course, 4 mA total idle current (each side). The supply current diminishes slightly with increasing temperature (about -0.03%/C). The total capacitance spanning the isolation barrier is less than 10 pF. The minimum period of a pulse that can be accurately coupled across the barrier is about 25 ns. Therefore the maximum square-wave frequency of operation is 20 MHz.
* * F0 (Rcv) F1 (Xmt) F2 (Xmt) F3 (Xmt) F4 (Xmt)
*Pin function is the same on all models, as shown in the AD261-0 column.
REV. 0
-5-
AD261
Logic information is sent across the barrier as "set-hi/set-lo" data that is derived from logic level transitions of the input. At power-up or after a fault condition, an output might not represent the state of the respective channel input to the isolator. An internal circuit operates in the background which interrogates all inputs about every 5 s and in the absence of logic transitions, sends appropriate "set-hi" or "set-lo" data across the barrier. Recovery time from a fault condition or at power-up is thus between 5 s and 10 s.
SCHMITT TRIGGER BUFFER DATA IN DQ DRIVER 3.5kV DATA OUTPUT ISOLATION BARRIER RECEIVER BUFFER OUT ENABLE
ENABLE
G GATED TRANSPARENT LATCH CONTINUOUS UPDATE CIRCUIT
Figure 1. Simplified Block Diagram
POSITIVE GOING INPUT THRESHOLD INPUT NEGATIVE GOING INPUT THRESHOLD
HYSTERESIS
OUTPUT
63% 37%
t ff
PROPAGATION DELAY
tPD = 14ns
BUFFER EFFECTIVE CIRCUIT MODEL DELAY LINE 14ns 5pF INPUT CAPACITANCE 5pF OUTPUT CAPACITANCE BUFFER 100
t rr = tff = 100 x CTOTAL OUTPUT CAPACITANCE
0.5ns - NO LOAD = 5.5ns INTO 50pF TOTAL DELAY = t PD
t rr = 13ns (NO LOAD), 18ns (50pF LOAD)
Figure 2. Typical Timing and Delay Models
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
22-Pin Plastic DIP (ND-22A)
0.550 (13.97) MAX 0.440 (11.18) MAX
15 22
1.500 (38.1) MAX
SIDE VIEW
1 8
END VIEW
0.160 (4.06) 0.140 (3.56)
0.050 (1.27)
0.020 0.010 (0.508 0.254) 16 PLACES
0.100 (2.54)
0.350 (8.89)
0.075 (1.91) PIN 1 BOTTOM VIEW 0.738* (18.75)
FIELD
0.250 (6.35)
SYSTEM
0.650 (16.51)
0.050 (1.27)
*CREEPAGE PATH (SUBTRACT APPROXIMATELY 0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD. THIS SPACING SUPPORTS THE INTRINSICALLY SAFE RATING OF 750V.
-6-
REV. 0
PRINTED IN U.S.A.
C3212-8-10/97

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